Labcenter Proteus Design Suite V6.6
Discussion Group, R4 Systems-Distributor
Tango to Ares conversion
|Tango2Ares.EXE||Tango Version 2.3 PCB converter to Ares region
file with net list
converter / comparator.
Current version: 1.01.02 (V6.9 region file breakdown)
|Instructions||Conversion steps and breakdowns of Tango and Ares data files|
|T_All.ZIP||Tango file with all element types represented for testing translation process|
|Tango2SDF.ZIP||Tango netlist to Ares SDF converter (From Labcenter website, I sugest the one embeded in Tango2Ares.exe!)|
6.9 SP5 Region file export/Import
1. Zones do not contain all the attributes available in Ares. Of the options available, only six make it into the flags section; no custom color info and only two of the five available types. Importing zones yields unusual results as in the custom color settings being set to black.
2. Zone "Custom" properties import randomly.
3. Zone "Suppress Islands" and "Route to this Zone" properties do not import.
4. Component lines and graphics elements in general are neither exported or imported with the line width and fill mode attributes intact.
5. All graphics are imported with the default settings imposed on them, i.e. default line widths and default fill=none.
6. The graphics paths, when exported, do not get their own CR+LF terminations but instead get the next line appended to the end.
7. Graphics tagged as "OC" (Occupancy) get loaded into the "ED" (Edge) layer.
8. Text exported to region file that contains quote marks ["] cuts off the text at import time at the first quote found (Second quote as far as Ares is concerned.)
1. Pad stacks allow, via style file writing, the use of surface pad shapes to define stack layers. Display and gerber output seem to be unaffected, however when editing such a pad stack, these layers show up as "None". This seems to be an issue with how Ares decides to show the layer as it does not populate any surface shapes in the drop down lists to begin with as opposed to the use of these stacks in designing the PWB.
2. Graphics translated as tracks (To maintain their original Tango widths) can't be selected in graphics mode and don't show in the track layer select list. They may however be selected, moved etc with a block select.
Tango pad shape translation:
Tango2Ares uses pad stacks in combination with polygonal surface pad shapes to replicate through hole pad shapes used in Tango exactly, Ares doesn't seem to have a problem with this except for the editing. The layers seem to operate normally however and the output of gerber data is not impeded. You have an option to do a closest fit just in case a problem arises at a later time: Surface pads are always replicated exactly using polygonal pad shapes.
|Isis Schematic Capture|
|Power Rail Assignement||Any net may be assigned as a power rail in ISIS, with the subsequent enhanced handling in ARES such as assigning a different net color and routing rules vs signal nets.|
|Reordering sheets||Don't use cut-n-paste to move blocks to new sheets to get the ordering right, just go to the sheet properties and edit the second box called "Sheet name". Isis numbers the sheets ROOT10, ROOT20 etc by default. To make ROOT20 come first, simply rename it to ROOT5 or rename ROOT10 to ROOT30 for the same effect.|
|Origin: Shortcut vs Icon||Use the "O" (or whatever you've switched it to) keyboard short cut to re-origin the schematic sheet. The icon method results in the 0,0 relative being set anywhere but where the mouse was clicked.|
|Homogenous Parts||Step by step to make multi-part homogenous symbols, i.e. quad NAND gates.|
|Standard title blocks||A-Size, B-Size, C-Size, D-Size|
|Ares PCB Layout|
|Memory Error / System||Program aborts when power plane inserted. If tracks that have a non-ground netlist association are connected to pads which are part of the ground net, inserting a ground plane will crash the program. This can happen if a block copy of tracks which were say connected to "+5v" are placed on top of pads which will be ground. This dissociation can be cleared by "Pretending" to edit the track in question at the pad which will associate it to the pad.|
|Guard Gap||Area around pads which will have solder mask (That green coating that covers what won't be soldered) removed. A 100th round pad with a 5th guard gap will sit in the center of a 110th hole in the solder mask.|
|Resist (Top/Bottom)||This is the green coating that covers areas not to be soldered. Called "Solder Mask" in the US.|
|Mask (Top/Bottom)||This defines the areas which will be coated with "Solder Paste" on which SMT components will be placed prior to reflow soldering. This artwork layer is usually etched, in negative, on a stainless steel sheet. Holes in the sheet allow solder paste to be applied to the SMT pads. Called a "Paste Mask" in the US|
|SMOBC||Solder Mask Over Bare Copper. Solder mask used to be placed on after the copper was tin or solder plated. During wave or reflow soldering, solder would flow under the mask and lift up or wrinkle the mask layer. Either large amounts of solder would be "Soaked" up or the mask would fail. SMOBC is now the standard.|
|Line styles||When creating components, select all lines and set the attributes to "Not Global" and desired width. This will prevent them from shifting if the global line width in the [System][Set template][Graphics] dialog is changed to control the font width on components. You can't edit the line styles for placed components.|
|Non attribute text in components||Text placed other than the Ref and Value attributes can't be moved or changed once a part is placed.|
|Attribute placement||Do not place the Reference and Value markers on top of the origin marker during component creation. This makes it hard to snap to the component origin without moving the attribute.|
|Auto Placement||The auto place function depends on a board outline being present. Any 2D closed area on the "Board" layer will do, including circles. DO NOT make your outline a triangle as this will crash the program losing any work you have done such as component assignment.|
|Update old board with new packages||Press [P] in the package list which brings up the library picker. Double click the selected part which will, if the part is already on the board, ask if you want to replace existing packages with the new one. This will only work if the old and new name is the same. If they are different, select the package on the board and edit its name... this will have the same effect but on a 1:1 basis. The same will happen if you edit a component and then re-save it on a layout with that package placed.|
|Pads on edge||Pads that touch the "Board Edge" will fail the DRC by 1/2 the width of the board edge graphic. Setting the width to 0 makes it disappear and no "Board Edge" upsets the auto placer. To get around this, place a non-zero board edge graphic to start and make the auto placer happy, then replace with one on Mech-4 to pass the DRC. (Or accept 4 DRC errors!)|
Holes and Slots
|Placing slots||The user must build a PadStack to produce a slotted hole in a board.|
|Library names||Ares does not seem to like the name "Diode" for a package library. I made an SMA diode symbol for one layout and tried to use it on the next but could not find it in any of the libraries. Ares simply didn't load it. Changing the name and restarting ARES made it visible again. On that note, all my libraries now are in the form "TES_xxxx.LIB".|
|Line width selection||To manually select from the track style box the trace width to route nets with, vs having the program use the default, uncheck [Tools][Auto track selection]|
|Connecting a package pad to a plane off netlist||(For things like grounding the tab pad of a TO220) Edit the pad to "Drill hole" only, place a large pad which touches both the edited hole and the plane, then remove the large pad. The clearances will fill in. Be careful that the pad is actually the same net as the plane, or simply add the extra hole to the schematic.|
||Pads larger than about 0.300 inches in diameter
have a copper coverage issue when a solid plane coinnection is required.
Just like when a gap is required, the plane is drawn around the pad as an
octagon and then filled from this edge out but an apparent error in the math
used to calculate the vertices of the octagon such that they lie ouside the
area of the pad leaves 8 small gaps open in the copper around the pad.
Second set is proposal to fix problem via difference in radius on which to compute vertices of octagon.
|Clearing planes||To prevent a plane from wrapping around corner mounting holes or filling areas to be kept clear or to clear areas in planes for things like part numbers etc, place a plane set to "Empty" in those areas.|
|Pads and Vias for plane stitching||Connecting ground planes with stitching vias can only be accomplished directly using "Pads" inserted into planes that are not net listed. If the plane is net listed, the relief dialog never comes up. This is done using the Relief list of the edit single pin dialog. To connect a via without relief to a net listed plane, run a track from a pad in the netlist to the via.|
|Changing the net of a pad used as a connection point for stitching vias.||If the method above is used, but the net of the pad to connect the vias changes its net (Say from ground to Vdd), before loading in a new netlist be sure to disconnect any of YOUR connections from the pad first. If you don't and then load a new netlist, all those vias and their tracks will be assigned the new net name and be isolated from the plane of the now different net.|
|Power plane generator||The board outline must be completely contiguous for the power plane generator tool to function properly. This may be either the rectangle 2D shape or a series of lines and/or arcs.|
|Font line width||The master line width for the Reference and Value attributes for components is in the [System][Set template][Graphics] menu. This sets the global width used for these attributes. Free text defaults to this value and can be over ridden, width and color, for the Vector font and color only for system fonts. If components are created with default 2d elements, the lines and text will both follow the global template unless dissociated from the global attributes first.|
|Photo Plots||Windows fonts do not photo plot cleanly so be sure to use Vector on physical layers and windows fonts on documentation layers.|
|Package Reference||To edit the size of the Reference and Value attributes of a package, right click the component to select it then left click the attribute. You may only edit height and kerning values, line width is a Template controlled global.|
|Good Plus signs||An aspect ratio of 2:1 is good for "+" signs on caps, ie 80Hx40W|
|Resist and Mask||These layers are negative.
Placing a filled circle on one of these layers is equivalent to placing a
hole of the same size in the gerber data.
1. What ever is manually inserted on the Resist layer will be combined in the negative with surface and through (Pad+(Guard Gap x2)) holes (Not viewable at design time so be sure to check the gerber!).
2. What ever is manually inserted on the Mask layer will be combined in the negative with surface pad sized holes (Not viewable at design time so be sure to check the gerber!).