/////////////////////////////////////////////////////////////
//Descrition:                                               /
//Firmware:     0125-00-00                                  /
//Hardware:     1199B                                       /
//Processor:    PIC18F6620                                  /
//Last Rev:     2003/06/15                                  /
/////////////////////////////////////////////////////////////
//Revision history                                          /
//00    2002/12/14  Initial release                         /
/////////////////////////////////////////////////////////////
#include "012500.h"
/////////////////////////////////////////////////////////////




/////////////////////////////////////////////////////////////
//This is a copy of the delay_ms code generated using CCS   /
//PICC V3.163 with a 9.3804mhz clock and the H4 mode set and/
//the following command lines:                              /
//#include <18F6620.h>                                      /
//#use delay(clock=39321600,RESTART_WDT)                    /
//                                                          /
//The resulting code, located at 0x9e, was a delay loop that/
//was either unstable or locked up.                         /
//                                                          /
//Analysis of the code indicated the problem was centered   /
//around the last decfsz instruction and was caused in some /
//way by the sequence of the following opcodes in concert   /
//with the position along a x0xx address boundry:           /
//  nop                                                     /
//  nop                                                     /
//  clrwdt                                                  /
//  decfsz  0xfef,f                                         /
//The problem occured as a result of the register not being /
//properly decremented during normal operation of the code  /
//but worked reliably during single stepping or when a break/
//paused execution between the nop and the clrwdt instruc-  /
//tions.  Once the lockup occured, programming for stanalone/
//mode and running without the ICD did not help.            /
//                                                          /
//A block start address of 0x009e fails                     /
//A block start address of 0x1000, 0x1001, 1002 fails       /
//A block start address of 0x1100 fixes the problem         /
//                                                          /
//changing the clock to HS does not fix the problem         /
//                                                          /
//2,6,7,8 nop's cause lock up of the decfsz                 /
//1,3,4,5,9 nop's seem to work (seems is operative word!)   /
//the correlation to nop count and function is 100% repeat- /
//able as is the address alignment of the block.  Replacing /
//the last clrwdt with a nop does not fix the problem.      /
//                                                          /
//replacing the nops with 'movlw 0x01's in any quantity or  /
//on any address alignment makes the problem go away        /
/////////////////////////////////////////////////////////////
#org 0x1000,0x11ff
void xdelay (){
#asm
delay:
CLRF   0xFEA
MOVLW  0x15
MOVWF  0xFE9
MOVF   0xFEF,W
BTFSC  0xFD8.2
GOTO   enddelay
dl3:
MOVLW  0x0C
MOVWF  0x01
dl2:
MOVLW  0xBF
MOVWF  0x00
dl1:
CLRWDT
DECFSZ 0x00,F
BRA    dl1
DECFSZ 0x01,F
BRA    dl2
MOVLW  0xBE
MOVWF  0x00
dl0:
DECFSZ 0x00,F
BRA    dl0      //adding a third nop or removing one makes it work
nop             //break here does not work (decrement does not work)
nop             //break here or single step through this section makes it work (decrement functions)
CLRWDT          //break here makes it work (decrement functions)
DECFSZ 0xFEF,F  //break here does not work (decrement does not work)
BRA    dl3
enddelay:
RETLW  00
#endasm
}


void main() {
/////////////////////////////////////////////////////////////
output_a(0x00);
output_b(0x00);
output_c(0x40);
output_d(0x00);
output_e(0x00);
output_f(0x00);
output_g(0x02);
//-----------------------------------------------------------
set_tris_a(0xCF);
set_tris_b(0xCF);
set_tris_c(0x80);
set_tris_d(0x00);
set_tris_e(0x00);
set_tris_f(0x02);
set_tris_g(0xE4);
/////////////////////////////////////////////////////////////
port_b_pullups(false);
/////////////////////////////////////////////////////////////
setup_adc_ports(ANALOG_AN0_TO_AN3);
setup_adc(ADC_CLOCK_INTERNAL);
setup_psp(PSP_DISABLED);
setup_spi(FALSE);
setup_wdt(WDT_OFF);
setup_timer_0(RTCC_INTERNAL);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DIV_BY_1,255,1);
setup_timer_3(T3_DISABLED|T3_DIV_BY_1);
setup_ccp1(CCP_PWM);
setup_ccp2(CCP_PWM);
setup_comparator(NC_NC_NC_NC);
setup_vref(FALSE);
//enable_interrupts(INT_RDA);
//enable_interrupts(INT_RDA2);
//enable_interrupts(global);


while(true){
//WWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW

output_low(monitor);
#asm
movlw  0x5
movwf  0x15
#endasm
xdelay();

output_high(monitor);
#asm
movlw  0x5
movwf  0x15
#endasm
xdelay();

//WWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWWW
}
}